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Si530/531
4
Rev. 1.0
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Period Jitter*
for FOUT < 160 MHz
JPER
RMS
—
1
—
ps
Peak-to-Peak
—
5
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. CLK± Output Phase Noise (Typical)
Configuration
fC
Output
81.25 MHz
LVDS
312.5 MHz
LVPECL
1066 MHz
LVPECL
Units
Offset Frequency (f)
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
L (f)
dBc/Hz
–110
–127
–134
–136
–143
–147
n/a
–100
–115
–119
–123
–135
–144
–147
–87
–102
–107
–111
–121
–135
–142
Table 7. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Units
Supply Voltage
VDD
–0.5 to +3.8
Volts
Input Voltage (any input pin)
VI
–0.5 to VDD + 0.3
Volts
Storage Temperature
TS
–55 to +125
C
ESD Sensitivity (HBM, per JESD22-A114)
ESD
>2500
Volts
Soldering Temperature (Pb-free profile)2
TPEAK
260
C
Soldering Temperature Time @ TPEAK (Pb-free profile)2
tP
10
seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions.
2. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including
soldering profiles.
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